(c) When U124 is in the read mode (RAM out- putting data), and U127
recognizes a binary 10,000,000 at pins 2 through 8 and 15, a negative-going pulse
appears at U127 pin 18. This pulse is lengthened and then output by U133 pin 6, which is
then applied to U133 pin 10, one input of an OR gate. The other input of this OR gate (pin
9) is driven by U134 pin 3. U134 produces a pulsing signal which controls the blink rate of
the QRS pulse while in the sinc mode.
(a) When the hold button is depressed, U131 pin 2 drives U128 pin 10,
U129 pin 23, and U127 pin 14 high. While U129 pin 23 is high, the pulses usually output
by U129 pin 8 are inhibited, allowing no further delayed signal to be output by U82 pin 1
(refer to paragraph 2-2d(7), Analog signal demultiplexer). If the sinc mode is enabled
during hold, the blinking of the QRS pulses is inhibited. The signal initiates a QRS blink at
U127 pin 18, which is held high during the hold.
(b) Finally, when U128 pin detects hold, U128's address counter is not
allowed to advance the 8 additional increments that it usually would while U128 pin 2 is
high. Because this counter is not incremented the eight additional counts, the trace on the
monitor appears to stand still. (Refer to paragraph 2-2d(5), Memory addressing.)
(a) The horizontal sweep ramp is derived from OP-AMP U83 pins 1, 2,
and 3, C93, R96, U81, and 081. When the horizontal retrace blanking pulse from U123
pin 16 goes low, Q81 conducts. This puts the bilateral switch between pins 3 and 4 of U81
(b) When the blanking pulse returns high, R96 starts charging C93. As
C93 charges, inverting amplifier U83 produces a positive-going linear ramp at pin 1. This
signal is then fed to the horizontal deflection circuit.
(11) Blanking. The horizontal retrace blanking pulse from U123 pin 16 and the
sinc mode QRS. blanking pulse from U133 pin 8 are logically added at U132 pins 5 and 4
respectively. The resulting low-going blanking signal from U132 pin 6 controls the CRT
(12) Vertical amplifier. The video signal from U80 pin 1 is fed to a low-pass
amplifier consisting of R92, C82 through C84, and U80 pins 5, 6, and 7. The output of
U80 pin 1 is coupled through C91 to the vertical gain control R231.
(13) Delayed analog signal. The output of U82 pin 1 is fed to a low-pass
amplifier consisting of R95, C88 through C90, and U82 pins 5, 6, and 7. The signal from
U82 pin 7 is coupled through C115 to the chart delay size control R141.