(e) When U123 pin 9 is high, the output drivers for U128 (pins 3 through
5 and 15 through 22) are enabled. When U128 is driving U124's address inputs, and
U123 pin 16 retrace blanking is high, U124 is outputting video data at it data outputs.
(f) The signal at U128 pin 23 increments U128's internal address
counter, thus providing sequential period (retrace blanking is high), U128's address
counter is incremented 1400 times.
(g) After the blanking signal is asserted (U123 pin 16 goes low), U123
pin 5 drives U128 pin 11 high. When this signal is high, U128's internal address counter is
allowed to increment at the 640kHz clock rate input to the device at pin 8. The pulse width
at pin 11 of U128 is long enough to allow the counter to advance another 400 locations.
(h) At this point, U128 is outputting the same address as it was at the
beginning of the previous horizontal scan. After U123 pin 5 goes low, U123 pin 6 drives
U128 pin 2 high. Just as when U128 pin 11 is high, a high state at pin 2 also allows
U128's internal counter to increment at the 640kHz clock rate. This pin, however, is high
only long enough to allow the counter to increment another 8 locations.
(i) When the next video display period (U123 pin 16 is high) begins, the
RAM will output data 8 locations past the location it started at during the previous video
display period. Additionally, because the video data starts 8 locations later, it will also end
8 locations later. Therefore, since the horizontal trace scans the screen from left to right,
the video data will appear to move from right to left.
Digital to analog.
(a) The circuit consists of an 8 bit latch U122, R/2R resistor network
R222, and OP-AMP U83. As RAM U124 outputs data, U122 latches it, making it available
to R222. U122 latches the data at its input pins on the rising edge of its clock input. Since
U122's outputs are permanently enabled, any data latched by the device immediately
appears at its output pins.
(b) R222 converts the digital data presented to it by U122 into an
equivalent analog value. This analog value is seen at R222 pin 1. U83 is configured as a
non-inverting voltage follower and, therefore, buffers the signal applied to it by R222.
(c) Random access memory (RAM) provides both video and delay data
to U122, depending on the state of U123 pin 9. (See memory addressing section.) Video
data are latched by U122 on the rising edge of the signal at U123 pin 15. Delay data are
latched by U122 on the rising edge of the signal at U123 pin 12. U123 pin 15 drives the
input at U129 pin 14 and U123 pin 12 drives the input at U129 pin. These two signals are
U122's clock input at pin 11. It should be noted that the analog signal output at U38 pin is
a multiplexed signal composed of the video data analog value and the delay data analog