Analog signal demultiplexer.
(a) The video and delay portions of the multiplexed analog signal from
U83 pin are separated by the switching on and off of two bilateral switches internal to U81.
As the signal at U123 pin 15 goes high, C80, R90, R91, and U84 pins 1, 2, and 3 level
adjust it to 8v. RA26, C81, and U84 pins 4, 5, and 6 delay the pulse. When U84 pin 4
drives U81 pin 13 high, the bilateral switch between pins 1 and 2 of U81 is put in the low-
(b) U85 now charges to the voltage present at U83 pin and voltage
follower U80 buffers the signal at pin 1. RA23, RA24, and RA25 bias U81 pin 3 to 2.5v.
The signal at U123 pin 15 is synchronized so that it turns on U81 pins 1 and 2 only when
the video portion of the analog signal is present at U83 pin. Therefore, the signal at U80
pin 1 is the video analog signal.
(c) As the signal at U129 pin 8 goes high, C86, R93, R94, and U84 pins
8, 9, and 10 level adjust it to 8v. RA21, C9, and U84 pins 11, 12, and 13 delay the
pulse. When U84 pin 11 drives U81 pin 6 high, the bilateral switch between pins 8 and 9
of U81 is forced into the low-impedance state. C87 now charges to the voltage present at
the U83 pin and voltage follower U82 buffers the signal at pin 1.
(d) RA22, RA23, and RA24 bias U82 pin 3 to 2.5v. The signal at U129
pin 8 is synchronized so that it turns on U81 pins 8 and 9 only when the delay portion of
the analog signal is present at U83 pin. Therefore, the signal at U82 pin 1 is the delayed
(a) Operating in the sinc mode, a QRS synchronous pulse is applied to
pin 1 of U127. When the rising edge of this pulse is detected, a register inside U127 is set.
Usually, when a pulse is applied to U127 pin 9, U127 inverts the pulse and inputs it at pin
16 and pin 1. However, if U127 receives a pulse on pin 9, and its internal sync register is
set, it inputs an inverted pulse at pin 1 but not pin 16.
(b) Because U121's outputs are not enabled during U124's (RAM) write
cycle, U124 is loaded with the binary sync word 10,000,000 (as determined by R220 and
R221) in place of the digitized value of the analog signal. When the pulse at U127 pin 1
rises, a positive-going pulse is applied to U127 pin 11. This pulse resets U127's internal
sync register, thus allowing pulses at U127 pin 16 to occur again.