(c) The logic level at pin 8 of U132, now high, passes through U133 pins
12 and 11 to U132 pins 12 and 13. Pin 11 of U132 drives the reset signal for U126 and,
indirectly, U130. This signal is fed back to U132 pin 10 to maintain the high state of U132
pin 8 for the duration of there set pulse.
(d) Immediately after power-up, R229 starts charging C226. After about
1 second, the logic lever at U132 pin 9 equals a valid logic low. At this time, pin 8 of U132
falls low followed by U133 pins 12 and 11, U132 pins 12, 13, 11, and U132 pin 10.
(e) A logic low is now present at U126 pin 11, and a logic high is present
at U130 pin 13. After this occurs, normal system operation can begin.
(a) Circuit timing originates with a 640kHz clock signal driven by U131
pin 8. This signal is divided at U130 pin 5 and fed to binary counter U126 pin 10. U126 is
a 12 bit binary counter which drives the address pins, A0 through A11, of U125.
(b) Besides providing A11 to U125, the signal from U126 pin 1 is inverted
and input to U130 at pin 11. This flip-flop divides its input signal by 2 at pin 9 and is then
used to generate A12 for U125.
(c) U125, an 8k x 8 EPROM, is permanently enabled. As U126 and
U130 increment U125's address pins, U125 provides a continuous flow of data to U123.
Latch U123 captures the data from U125 on the rising edge of its clock input (pin 11).
(d) This clock input is driven by the 640kHz signal originating from U131
pin 8. The eight outputs of U123, Q0 through Q7, provide the general synchronized timing
signals used by the rest of the circuit.
(e) At pin 19 of U123, Q7, a high-going pulse passes through U133 pins
13 and 11 to U132 pins 12 and 13. This signal, driven by U132 pin 11, resets U126 at its
pins 11 and 15 and inverted by U131 pins 13 and 12 to produce a low-going pulse which
resets U130 at pin 13. Resetting these devices at the end of each timing sequence
automatically starts the timing sequence again, providing continuous timing signals at the
outputs of U123.
Analog to digital.
(a) The analog to digital (A/D) converter U120 is an 8 bit successive
approximation device. It samples the incoming analog signal eight times per horizontal
sweep (400 times per second). The write command, a low-going pulse at U120 pin 3, is
received from Programmable Array Logic (PAL) device U127 pin 17. This write pulse is an
inversion of the pulse received by U127 at pin 9.