(c) When in the RAM read mode, U124 is usually outputting video data.
Video data will be discussed in the memory addressing section. When U123 pin 9 goes
low A, the RAM stops outputting video data. Delay data will be discussed in the memory
(d) Shortly afterward, U123A pin 12 goes high B. This signal is
immediately available to U132A pin 1, but delayed due to R224 and C221, to U132 pin 2.
This produces a delayed high-going pulse at U132A pin 3.
(e) This high state is seen by U124 at pin 20 (OE), disabling U124's data
output drivers. The pulse from U132 pin 3 also feeds U127 pin 9. As explained in the A/D
section, this now allows U121 to present the RAM with the digitized value of the incoming
analog signal. When U132 pin 3 goes high C, U131 pin 4 goes low. As R225 charges
C222, the voltage at U131 pin 3 will reach a valid logic low level. At this point, U131 pin 4
will go high D. The RAM is now in a RAM write cycle. Note that the following will occur
before U132 pin 3 goes low E.
(f) When the low to high transition D is seen at U124 pin 21 (WR), the
data presented to the RAM by U121 will be written into it. When U123 pin 9 returns high,
the RAM write cycle is completed, and U124 resumes its normal mode of operation.
(a) There are two devices which alternately drive the address lines of
U124. U128 drives the RAM address pins when U124 is outputting video data. When the
RAM is outputting delay data, and when data is being written to U124, U129 is driving the
(b) The state of U123 pin 9 determines which device is driving U124's
address pins. When U123 pin 9 is high, U128 is driving U124's address inputs and U129's
outputs are tri-stated. The opposite situation exists when U123 pin 9 is low.
(c) When U123 pin 9 drives U129 pin 2 low, U129 outputs an address on
its pins 3 through 5 and 15 through 22. Upon receiving this address, U124 will drive its
data lines with the data stored at that address location. The data which U124 outputs
when U129 is driving its address bus is known as delay data. After a short time, U124's
data outputs are disabled, and new data from the A/D converter is written into RAM at the
same address location.
(d) When pin 2 to U129 returns high, U129's address outputs are again
disabled. At the same time, the devices' internal counter is incremented by one so that the
next time its outputs are enabled, the next sequential address appears at its address pins.
After the counter increments to 1799, it automatically resets itself to zero and starts to